1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a nonvolatile semiconductor memory, a method for manufacturing the same, and a method of using the same.
2. Description of Related Art
A nonvolatile semiconductor memory represented by for example, by a flash EEPROM (electrically erasable programmable read only memory), has a capability of electrically writing, erasing and reading memory cells provided therein. A typical memory cell is composed of a single electric field effect transistor including a floating gate, a second gate insulator film and a control gate which are formed in the named order on a channel region defined between a source and a drain formed in a surface of a semiconductor substrate, the control gate being capacitively coupled with the floating gate through the second gate insulator film. The memory cell of this structure can store data by allocating "0" and "1" to different thresholds attributable to different charge storage conditions of the floating gate.
With a recently widened utilization of the nonvolatile semiconductor memory, a demand for a nonvolatile semiconductor memory having a high integration density is increasing, in order to miniaturize a system or apparatus incorporating therein the nonvolatile semiconductor memory, and in order to lower the cost per bit of stored information. For the purpose of meeting this demand, there has been proposed a new nonvolatile semiconductor memory having a plurality of floating gates, different from the conventional nonvolatile semiconductor memory as mentioned above.
For example, Japanese Patent Application Laid-open Publication No. JP-A-62-094987 proposes an electric field effect transistor (memory cell) as shown in FIG. 1 (called a "first prior art example" hereinafter). Namely, the shown electric field effect transistor includes a P-type semiconductor substrate 10 having a drain 11 and a source 12 formed on a principal surface thereof to define a channel 10A therebetween, and a first floating gate 16 and a second floating gate 15 which are formed, separately from each other in a direction parallel to the principal surface of the substrate, on a first gate insulator 13 formed on the channel 10A. Furthermore, a second gate insulator film 14 is formed to cover the first floating gate 16 and the second floating gate 15, and a control gate 17 is formed on the second gate insulator film 14, so that the control gate 17 capacitively coupled with each of the first floating gate 16 and the second floating gate 15 through the second gate insulator film 14.
With this arrangement, a reading current of four different levels can be obtained dependent upon whether or not an electric charge is stored in the first floating gate 16 and upon whether or not an electric charge is stored in the second floating gate 15. Thus, data of two bits can be stored by allocating the four different levels of the reading current to "00", "01", "10" and "11", respectively. In other words, it may be said that a multi-bit memory cell can be realized.
Furthermore, Japanese Patent Application Laid-open Publication No. JP-A-1-212472 proposes an electric field effect transistor (memory cell) as shown in FIG. 2 (called a "second prior art example" hereinafter). Namely, the shown electric field effect transistor includes two floating gates 6S and 6D, similar to the first prior art example mentioned above, and a control gate 8 formed to cover the two floating gates 6S and 6D in an insulating relation. Similarly to the first prior art example, a reading current of four different levels can be obtained dependent upon whether or not an electric charge is stored in the first floating gate 16 and upon whether or not an electric charge is stored in the second floating gate 15. Thus, data of two bits can be stored by allocating the four different levels of the reading current to "00", "01", "10" and "11", respectively. Namely, a multi-bit memory cell is realized.
The memory cell of this second prior art example can be written by applying a positive voltage to the control gate 8 and one of a source and a drain, and grounding the other of the source and the drain, so that channel hot electrons are generated and injected into the selected floating gate. On the other hand, data can be erased by irradiating an ultraviolet ray to the memory cell so that the electrons trapped in the floating gates are discharged.
The above mentioned prior art semiconductor memories have various problems. A first problem is that, if a method for manufacturing the nonvolatile semiconductor memories composed of memory cells having the two floating gates is estimated, a gate length of each memory cell cannot be made less than three times a limit length (design standard) of a photolithography.
The reason for this is as follows: Since it is desirable to simultaneously form the first floating gate and the second floating gate by patterning the same polysilicon layer by the same photolithographic step, a distance between the source and the drain is required to have a total length of a length of the first floating gate, a distance between the first floating gate and the second floating gate, and a length of the second floating gate.
A second problem is that a large current is required for a writing operation in the nonvolatile semiconductor memories composed of memory cells having the two floating gates, and therefore, it is difficult to realize a low voltage operation of the nonvolatile semiconductor memory.
The reason is that: The memory cell writing is carried out by applying a positive voltage to the control gate and one of the source and the drain and grounding the other of the source and the drain and the substrate, so that channel hot electrons are generated in a pinch-off region in proximity of the source or the drain applied with the positive voltage, and the generated channel hot electrons are injected into the floating gate. However, an injection coefficient defined by a ratio of a gate current to a channel current is as low as about 10.sup.-6, and therefore, a very large channel current is required. For example, in the case of a memory cell having the gate length of 1 .mu.m, the channel current of several milliamperes is required in the writing operation, and therefore, a large peripheral circuit is required in the memory device.